Home » Source Code » SPI Verilog code with programmable clock

SPI Verilog code with programmable clock

tiangao
2010-08-18 19:38:17
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Category Category:
VHDL-FPGA-VerilogVHDL-FPGA-Verilog VHDLVHDL

Description

SPI Verilog code with programmable clock
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format2.00 B2009-04-07 13:04
01.96 kB
01.96 kB
01.96 kB
spi_slave_model.v.svn-base3.55 kB2009-04-07 13:04
tb_spi_top.v.svn-base12.40 kB2009-04-07 13:04
wb_master_model.v.svn-base5.59 kB2009-04-07 13:04
01.96 kB
01.96 kB
01.96 kB
01.96 kB
spi_slave_model.v3.55 kB2009-04-07 13:04
tb_spi_top.v12.40 kB2009-04-07 13:04
wb_master_model.v5.59 kB2009-04-07 13:04
01.96 kB
01.96 kB
all-wcprops170.00 B2009-04-07 13:04
entries384.00 B2009-04-07 13:04
format2.00 B2009-04-07 13:04
01.96 kB
spi.pdf.svn-base53.00 B2009-04-07 13:04
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spi.pdf.svn-base76.90 kB2009-04-07 13:04
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spi.pdf76.90 kB2009-04-07 13:04
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all-wcprops178.00 B2009-04-07 13:04
entries379.00 B2009-04-07 13:04
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01.96 kB
spi.doc.svn-base79.00 B2009-04-07 13:04
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spi.doc.svn-base226.50 kB2009-04-07 13:04
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spi.doc226.50 kB2009-04-07 13:04
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all-wcprops77.00 B2009-04-07 13:04
entries234.00 B2009-04-07 13:04
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all-wcprops630.00 B2009-04-07 13:04
entries966.00 B2009-04-07 13:04
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01.96 kB
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01.96 kB
spi_clgen.v.svn-base4.99 kB2009-04-07 13:04
spi_defines.v.svn-base6.19 kB2009-04-07 13:04
spi_shift.v.svn-base9.22 kB2009-04-07 13:04
spi_top.v.svn-base12.21 kB2009-04-07 13:04
timescale.v.svn-base23.00 B2009-04-07 13:04
01.96 kB
01.96 kB
01.96 kB
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spi_clgen.v4.99 kB2009-04-07 13:04
spi_defines.v6.19 kB2009-04-07 13:04
spi_shift.v9.22 kB2009-04-07 13:04
spi_top.v12.21 kB2009-04-07 13:04
timescale.v23.00 B2009-04-07 13:04
01.96 kB
01.96 kB
all-wcprops77.00 B2009-04-07 13:04
entries234.00 B2009-04-07 13:04
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01.96 kB
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all-wcprops85.00 B2009-04-07 13:04
entries238.00 B2009-04-07 13:04
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all-wcprops400.00 B2009-04-07 13:04
entries667.00 B2009-04-07 13:04
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01.96 kB
run_sim.svn-base30.00 B2009-04-07 13:04
01.96 kB
01.96 kB
rtl.fl.svn-base34.00 B2009-04-07 13:04
run_sim.svn-base3.07 kB2009-04-07 13:04
sim.fl.svn-base49.00 B2009-04-07 13:04
01.96 kB
01.96 kB
01.96 kB
01.96 kB
rtl.fl34.00 B2009-04-07 13:04
run_sim3.07 kB2009-04-07 13:04
sim.fl49.00 B2009-04-07 13:04
01.96 kB
01.96 kB
all-wcprops79.00 B2009-04-07 13:04
dir-prop-base28.00 B2009-04-07 13:04
entries229.00 B2009-04-07 13:04
format2.00 B2009-04-07 13:04
01.96 kB
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SPI Verilog code with programmable clock (5.20 MB)

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