DDR (double rate) SDRAM controller reference design Verilog code, can be directl...


  VHDL-FPGA-Verilog    VHDL   

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Download Source Codes:   DDR_SDRAM_verilog.ra (734.83 kB)  

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DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good

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Project Files

NameSizeDate


 ddr_sdram.pdf461.72 kB30-05-00 09:59


 mt46v4m16.v43.90 kB29-03-00 21:36


 ddr_sdram.csf10.12 kB02-06-00 15:03


 ddr_sdram.esf618.00 B02-06-00 15:02


 ddr_sdram.psf2.39 kB02-06-00 15:03


 ddr_sdram.quartus194.00 B02-06-00 15:03


 ddr_sdram.vqm581.37 kB22-05-00 13:06


 pll1.v4.54 kB20-05-00 12:02


 ddr_compile_all.v213.00 B20-05-00 12:07


 ddr_sdram_tb.v17.93 kB19-05-00 17:58


 modelsim.ini7.55 kB21-05-00 20:51


 readme.txt377.00 B23-05-00 03:52


 verilog.psm20.19 kB21-05-00 23:21


 _primary.dat2.28 kB21-05-00 23:21


 _primary.vhd899.00 B21-05-00 23:21


 verilog.psm45.15 kB21-05-00 23:21


 _primary.dat5.01 kB21-05-00 23:21


 _primary.vhd1.30 kB21-05-00 23:21


 verilog.psm21.21 kB21-05-00 23:21


 _primary.dat2.72 kB21-05-00 23:21


 _primary.vhd1.09 kB21-05-00 23:21


 verilog.psm23.52 kB21-05-00 23:21


 _primary.dat3.14 kB21-05-00 23:21


 _primary.vhd817.00 B21-05-00 23:21


 verilog.psm27.97 kB21-05-00 23:21


 _primary.dat4.45 kB21-05-00 23:21


 _primary.vhd1.06 kB21-05-00 23:21


 verilog.psm60.30 kB21-05-00 23:21


 _primary.dat9.18 kB21-05-00 23:21


 _primary.vhd102.00 B21-05-00 23:21


 verilog.psm226.59 kB21-05-00 23:21


 _primary.dat24.52 kB21-05-00 23:21


 _primary.vhd1.15 kB21-05-00 23:21


 verilog.psm4.78 kB21-05-00 23:21


 _primary.dat823.00 B21-05-00 23:21


 _primary.vhd256.00 B21-05-00 23:21


 _info1.08 kB21-05-00 23:21


 altclklock.v9.06 kB20-05-00 12:03


 ddr_Command.v16.20 kB02-06-00 12:08


 ddr_control_interface.v9.20 kB02-06-00 12:06


 ddr_data_path.v9.22 kB23-05-00 13:56


 ddr_sdram.v8.86 kB23-05-00 13:55


 Params.v1.02 kB02-06-00 12:27


 pll1.v4.54 kB20-05-00 12:02


 ddr_data_path.srm459.19 kB20-05-00 13:22


 ddr_data_path.srr62.96 kB20-05-00 13:22


 ddr_data_path.srs28.71 kB20-05-00 13:17


 ddr_data_path.tlg3.50 kB20-05-00 13:17


 ddr_data_path.xrf112.90 kB20-05-00 13:22


 ddr_sdram.prj1.15 kB22-05-00 13:07


 ddr_sdram.sdc428.00 B20-05-00 13:22


 ddr_sdram.srm458.93 kB22-05-00 13:06


 ddr_sdram.srr73.41 kB22-05-00 13:06


 ddr_sdram.srs29.23 kB22-05-00 08:23


 ddr_sdram.tcl455.00 B22-05-00 13:06


 ddr_sdram.tlg3.50 kB22-05-00 08:23


 ddr_sdram.vqm581.37 kB22-05-00 13:06


 ddr_sdram.xrf112.41 kB22-05-00 13:06


 ddr_sdram_cons.tcl194.00 B22-05-00 13:06


 ddr_sdram_rm.tcl979.00 B22-05-00 13:06


 readme.txt563.00 B02-06-00 12:04


 <altclklock>0.00 B23-05-00 13:49


 <ddr_command>0.00 B23-05-00 13:49


 <ddr_control_interface>0.00 B23-05-00 13:49


 <ddr_data_path>0.00 B23-05-00 13:49


 <ddr_sdram>0.00 B23-05-00 13:49


 <ddr_sdram_tb>0.00 B23-05-00 13:49


 <mt46v4m16>0.00 B23-05-00 13:49


 <pll1>0.00 B23-05-00 13:49


 <work>0.00 B23-05-00 13:49


 <synplicity>0.00 B23-05-00 13:49


 <doc>0.00 B02-06-00 09:26


 <model>0.00 B23-05-00 13:48


 <route>0.00 B02-06-00 15:04


 <simulation>0.00 B02-06-00 12:15


 <source>0.00 B02-06-00 12:27


 <synthesis>0.00 B23-05-00 13:58



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