Verilog pulse generator source code, can be used to simulate three-phase AC zero crossing, mainly us
2016-08-22
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Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
vhdl
verilog
脉冲
发生器
源代码
用于
模拟
零点
主要
调试
一些
svc
控制器
算法
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