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Viterbi decoder。Verilog

  VHDL-FPGA-Verilog    VHDL   

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Download Source Codes:   Viterbi_decoder.rar (63.32 kB)  

Viterbi decoder。Verilog

Name
Size
Date
 acs.v
9.64 kB
13-02-01 04:20
 bmg.v
3.77 kB
13-02-01 04:20
 control.v
2.66 kB
13-02-01 04:20
 decoder.v
2.53 kB
13-02-01 04:20
 dff.v
416.00 B
13-02-01 04:20
 mmu.v
4.05 kB
13-02-01 04:20
 params.v
1.26 kB
13-02-01 04:20
 ram.v
9.86 kB
13-02-01 04:20
 tbu.v
2.24 kB
13-02-01 04:20
 testbench.v
14.35 kB
13-02-01 04:20
 viterbi_encode9.v
1.19 kB
13-02-01 04:20
 <Viterbi>
0.00 B
Hard Decision
 viterbi译码文档.pdf
57.97 kB
23-01-07 08:37
 使用说明请参看右侧注释====〉〉.txt
774.00 B
28-01-08 15:31
 <Viterbi译码器的编解码器的设计>
0.00 B
26-08-09 09:33

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