Simple Full Adder Verilog Code
2016-08-23
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This is a simple 1 bit full adder verilog code
`timescale 1ns / 1ps
module 1BitFullAdder (input a,
input b,
input cin,
output s,
output cout );
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
//Test Bench
verilog
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