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iic master

2013-09-29 10:55:06
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verilogverilog Verilog HDLVerilog


FPGA validation IIC master · · EEPROM read/write operation to succeed

Frequency clock clk_div:FPGA Board to meet the SCL clock line speeds up to 400KB

Main_state.v: top level state machines, control master interfaces throughout the process of

Scl_generator.v:Master interface, SCL state machine generator and master the interface state machine consists of two parts

Mainsmtb.v: in the context of ModelSim simulation of excitation

Top.v design top modules

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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
clk_div.v822.00 B12-04-13 10:23
mainsmtb.v844.00 B09-04-13 17:35
main_state.v18.80 kB12-04-13 09:40
scl_generator.v17.97 kB12-04-13 10:17
top.v4.15 kB09-04-13 17:35
<ramdom>0.00 B0 0
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iic master (8.00 kB)

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