Asynchronous clock domain crossing fifo design
2016-08-23
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Asynchronous clock domain crossing design a FIFO fifo design is one of the most common problems encountered by ASIC designers. This article focuses on how
Sample design FIFO-- This is a deceptively simple but complex task.
The outset, we should note, FIFO is typically used transition clock domains, is a dual clock design. In other words,
Design Engineering be processed (work off) two clocks, and therefore, in most cases, FIFO operates independently
Between the two clocks. However, we do not start from such a structure introduced - we will work in a single clock
A FIFO special case begins. While working in the same clock FIFO is rarely used in practice,
But it is more complex designs to build a platform, which is very useful
Sample design FIFO-- This is a deceptively simple but complex task.
The outset, we should note, FIFO is typically used transition clock domains, is a dual clock design. In other words,
Design Engineering be processed (work off) two clocks, and therefore, in most cases, FIFO operates independently
Between the two clocks. However, we do not start from such a structure introduced - we will work in a single clock
A FIFO special case begins. While working in the same clock FIFO is rarely used in practice,
But it is more complex designs to build a platform, which is very useful
verilog
fifo
设计
异步
时钟
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