half-adder
2016-08-23
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it contain VHDL half -adder with test-bench
test-bench means 'project maker can announce what time shall he give a term
for example
a <= '0', '1' after 5ns, '0' after 10ns, '1' after 15ns, '0' after 20ns, '1' after 25ns, '0' after 30ns, '1' 35ns;
b <= '0', '1' after 10ns , '0' after 20ns, '1' after 30ns, '0' after 40ns;
vhdl
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