FPGA'for' cycle
2016-08-23
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Written in the Verilog language for circulation and used to verify whether in the FPGA can writing a for loop in c, it turned out although the emulation to get the right result, but in real engineering are not compile-time takes 24 hours to complete, so I chose another method to loop through, after all, the FPGA is parallel, and c is the serial.
verilog
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