Home » Source Code » DDR2 controller, Verilog source code

DDR2 controller, Verilog source code

imba6450
2013-10-30 23:51:18
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Download(s): 12
Point (s): 3 
Category Category:
verilogverilog Verilog HDLVerilog

Description

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
altclklock.v3.55 kB12-11-10 11:41
ͼ9-16.bmp487.67 kB12-11-10 11:42
ͼ9-17.bmp527.02 kB12-11-10 11:42
ͼ9-19.bmp501.29 kB12-11-10 11:42
ͼ9-20.bmp518.47 kB12-11-10 11:42
ͼ9-22.bmp573.22 kB12-11-10 11:42
ͼ9-23.bmp465.43 kB12-11-10 11:42
ͼ9-26.bmp530.44 kB12-11-10 11:42
ͼ9-27.bmp530.44 kB12-11-10 11:42
ddr.cr.mti2.53 kB12-11-10 11:41
ddr.mpf19.13 kB12-11-10 11:41
ddr_Command.v13.18 kB12-11-10 11:41
ddr_control_interface.v7.12 kB12-11-10 11:41
ddr_data_path.v7.42 kB12-11-10 11:41
ddr_sdram.v7.52 kB12-11-10 11:41
ddr_sdram_tb.v14.71 kB12-11-10 11:41
note.txt82.00 B12-11-10 11:41
Params.v311.00 B12-11-10 11:41
pll1.v989.00 B12-11-10 11:41
transcript503.00 B12-11-10 11:41
vsim.wlf1.18 MB12-11-10 11:41
ddr_command.bmp2.36 MB12-11-10 11:42
ddr_control_interface.bmp1.93 MB12-11-10 11:42
ddr_data_path.bmp2.36 MB12-11-10 11:42
ddr_sdram.bmp2.36 MB12-11-10 11:42
ddr_sdram_tb.bmp2.09 MB12-11-10 11:42
verilog.asm22.50 kB12-11-10 11:41
_primary.dat2.28 kB12-11-10 11:41
_primary.vhd899.00 B12-11-10 11:41
verilog.asm39.68 kB12-11-10 11:41
_primary.dat5.01 kB12-11-10 11:41
_primary.vhd1.30 kB12-11-10 11:41
verilog.asm21.15 kB12-11-10 11:41
_primary.dat2.72 kB12-11-10 11:41
_primary.vhd1.09 kB12-11-10 11:41
verilog.asm20.14 kB12-11-10 11:41
_primary.dat3.10 kB12-11-10 11:41
_primary.vhd817.00 B12-11-10 11:41
verilog.asm29.30 kB12-11-10 11:41
_primary.dat4.45 kB12-11-10 11:41
_primary.vhd1.06 kB12-11-10 11:41
verilog.asm63.93 kB12-11-10 11:41
_primary.dat9.18 kB12-11-10 11:41
_primary.vhd84.00 B12-11-10 11:41
verilog.asm244.17 kB12-11-10 11:41
_primary.dat24.52 kB12-11-10 11:41
_primary.vhd1.15 kB12-11-10 11:41
transcript524.00 B12-11-10 11:41
verilog.asm5.45 kB12-11-10 11:41
_primary.dat823.00 B12-11-10 11:41
_primary.vhd256.00 B12-11-10 11:41
_info1.48 kB12-11-10 11:41
<altclklock>0.00 B12-11-10 11:41
<ddr_command>0.00 B12-11-10 11:41
<ddr_control_interface>0.00 B12-11-10 11:41
<ddr_data_path>0.00 B12-11-10 11:41
<ddr_sdram>0.00 B12-11-10 11:41
<ddr_sdram_tb>0.00 B12-11-10 11:41
<mt46v4m16>0.00 B12-11-10 11:41
<pll1>0.00 B12-11-10 11:41
<chart>0.00 B12-11-10 11:42
<wave>0.00 B12-11-10 11:42
<work>0.00 B12-11-10 11:41
<9.2>0.00 B12-11-10 11:41
...
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Comments

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Minimum:15 words, Maximum:160 words
sccdzhangx1017813
2015-02-02

这个资料感觉不错,学习中,希望对开发有帮助

tao362055143
2015-04-28

额,貌似不太全吧。我怎么没看到MT46V4M16这个文件

留侯
2015-05-26

利用verilog编写的ddr2控制器,实现了ddr2的读写功能

1630110121
2016-01-29

这个资料感觉不错,学习中,希望对开发有帮助,感谢感谢

1601015340
2016-03-24

这个资料非常有用,学习学习,希望对自己的项目有帮助

wqh1988
2017-02-08

这个是基于xilinx FPGA做的代码 ,我用的是altera 不过都是类似的,我先移植下试玩效果后再上传给大家分享

zy512
2017-03-08

不错的资源,学习一下,谢谢分享【需要的朋友可以看我用户名联系我】

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DDR2 controller, Verilog source code (1.16 MB)

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