DDR2 controller, Verilog source code
2016-08-23
6 0 0
4.1
Other
Earn points
Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
verilog
源码
DDR
控制器
Related Source Codes
AXI Host Slave Function Model
0
0
no vote
Axi slave to fifo code
0
0
no vote
DMA Controller Based on AHB
0
0
no vote
Verilog implementation of ldpc code
0
0
no vote
Minimum sum decoding
0
0
no vote
No comment