verilog and vhdl files
2016-08-23
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tff1 is
port(
clk: in std_logic;
rst: in std_logic;
q1: out std_logic);
end tff1;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tff1 is
port(
clk: in std_logic;
rst: in std_logic;
q1: out std_logic);
end tff1;
vhdl
语言
文件
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