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Xilinx IIC IP

2013-11-28 03:54:37
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EmbededEmbeded VHDLVHDL


IIC interfaces provided by Xilinx, AXI interface.

‧ AXI interface is based on the AXI4-Lite interface
‧ Master or slave operation
‧ Multi-master operation
‧ Software selectable acknowledge bit
‧ Arbitration lost interrupt with automatic mode switching from master to slave
‧ Calling address identification interrupt with automatic mode switching from master to slave
‧ START and STOP signal generation and detection
‧ Repeated START signal generation
‧ Acknowledge bit generation and detection
‧ Bus busy detec
‧ Fast mode 400 KHz operation or standard mode 100 KHz
‧ 7-bit or 10-bit addressing
‧ General call enable or disable
‧ Transmit and receive FIFOs - 16 bytes deep
‧ Throttling
‧ General purpose output, 1 bit to 8 bits wide
‧ Dynamic Start and Stop generation
‧ Filtering on the SCL and SDA signals to eliminate spurious pulses

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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
01.97 kB
01.97 kB
bd.tcl1.20 kB2013-06-12 10:21
component.xml47.50 kB2013-06-12 10:21
01.97 kB
axi_iic_v2_0_changelog.txt2.42 kB2013-06-12 10:21
01.97 kB
01.97 kB
01.97 kB
axi_iic.vhd12.70 kB2013-06-12 10:21
axi_ipif_ssp1.vhd21.51 kB2013-06-12 10:21
debounce.vhd9.52 kB2013-06-12 10:21
dynamic_master.vhd15.84 kB2013-06-12 10:21
filter.vhd8.90 kB2013-06-12 10:21
iic.vhd28.01 kB2013-06-12 10:21
iic_control.vhd85.80 kB2013-06-12 10:21
iic_pkg.vhd10.22 kB2013-06-12 10:21
reg_interface.vhd56.83 kB2013-06-12 10:21
shift8.vhd6.97 kB2013-06-12 10:21
upcnt_n.vhd6.87 kB2013-06-12 10:21
01.97 kB
ooc.ttcl312.00 B2013-06-12 10:21
01.97 kB
01.97 kB
board.xit726.00 B2013-06-12 10:21
utils.tcl8.18 kB2013-06-12 10:21
01.97 kB
axi_iic_upgrades.tcl350.00 B2013-06-12 10:21
axi_iic_v2_0.tcl10.63 kB2013-06-12 10:21
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Xilinx IIC IP (66.70 kB)

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