Home » Source Code » I2C Slave AND I2C Master

I2C Slave AND I2C Master

jinchengji
2013-11-26 10:28:10
The author
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Download(s): 9
Point (s): 2 
Category Category:
verilogverilog Verilog HDLVerilog

Description

I2C Slave is inside and the I2C Master and contain the emulator as well as wave files, I took a look at, particularly easy to understand
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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
01.97 kB
01.97 kB
I2CSlave.prd264.00 B2006-11-15 19:19
I2CSlave.prj1.30 kB2006-11-15 19:19
I2Cslave.v9.15 kB2006-11-16 10:33
myram.v386.00 B2006-11-16 10:25
01.96 kB
<.recordref>0.00 B2006-11-15 18:28
AutoConstraint_I2Cslave.sdc176.00 B2006-11-15 22:10
AutoConstraint_myRAM.sdc173.00 B2006-11-15 18:28
I2Cslave.edf65.37 kB2006-11-15 22:10
I2Cslave.fse503.00 B2006-11-15 22:10
I2Cslave.htm336.00 B2006-11-15 22:10
I2Cslave.ncf459.00 B2006-11-15 22:10
I2Cslave.srd31.63 kB2006-11-15 22:10
I2Cslave.srm59.23 kB2006-11-15 22:10
I2Cslave.srr21.05 kB2006-11-15 22:10
I2Cslave.srs10.90 kB2006-11-15 22:10
I2Cslave.tlg380.00 B2006-11-15 22:10
myram.edf17.03 kB2006-11-15 18:28
<myram.fse>0.00 B2006-11-15 18:28
myram.htm324.00 B2006-11-15 19:19
myram.ncf591.00 B2006-11-15 18:28
myram.srd7.31 kB2006-11-15 18:28
myram.srm15.57 kB2006-11-15 18:28
myram.srr13.92 kB2006-11-15 18:28
myram.srs2.21 kB2006-11-15 18:28
myram.tlg187.00 B2006-11-15 18:28
rpt_I2Cslave.areasrr2.05 kB2006-11-15 22:10
rpt_I2Cslave_areasrr.htm2.49 kB2006-11-15 22:10
rpt_myRAM.areasrr2.03 kB2006-11-15 18:28
rpt_myRAM_areasrr.htm2.45 kB2006-11-15 18:28
rpt_slave_top.areasrr2.06 kB2006-11-13 16:06
rpt_slave_top_areasrr.htm2.49 kB2006-11-13 16:06
slave_top.edf1.09 kB2006-11-13 16:06
<slave_top.fse>0.00 B2006-11-13 16:06
slave_top.htm340.00 B2006-11-15 13:45
slave_top.ncf246.00 B2006-11-13 16:06
slave_top.srd1.19 kB2006-11-13 16:06
slave_top.srm1.23 kB2006-11-13 16:06
slave_top.srr4.43 kB2006-11-13 16:06
slave_top.srs2.04 kB2006-11-13 16:06
slave_top.tlg1.46 kB2006-11-13 16:06
01.96 kB
I2Cslave.msg830.00 B2006-11-15 22:10
I2Cslave.plg493.00 B2006-11-15 22:10
I2Cslave_flink.htm795.00 B2006-11-15 22:10
I2Cslave_srr.htm22.93 kB2006-11-15 22:10
I2Cslave_toc.htm1.36 kB2006-11-15 22:10
myram.msg970.00 B2006-11-15 18:28
myram.plg505.00 B2006-11-15 18:28
myram_flink.htm795.00 B2006-11-15 19:19
myram_srr.htm14.94 kB2006-11-15 19:19
myram_toc.htm1.32 kB2006-11-15 19:19
<slave_top.msg>0.00 B2006-11-13 16:07
slave_top.plg208.00 B2006-11-13 16:06
slave_top_flink.htm507.00 B2006-11-15 13:45
slave_top_srr.htm6.78 kB2006-11-15 13:45
slave_top_toc.htm855.00 B2006-11-15 13:45
timescale_flink.htm358.00 B2006-11-13 16:05
timescale_srr.htm711.00 B2006-11-13 16:05
timescale_toc.htm439.00 B2006-11-13 16:05
timescale.htm340.00 B2006-11-13 16:05
timescale.srr579.00 B2006-11-13 16:05
traplog.tlg1.91 kB2006-11-15 18:28
01.96 kB
I2Cslave.vif2.24 kB2006-11-15 22:10
myram.vif1.27 kB2006-11-15 18:28
slave_top.vif1.38 kB2006-11-13 16:06
01.96 kB
all.do3.06 kB2006-11-15 22:03
i2c_master_bit_ctrl.v17.08 kB2006-09-04 17:08
i2c_master_byte_ctrl.v10.30 kB2004-02-18 19:40
i2c_master_defines.v3.14 kB2001-11-05 19:59
i2c_master_top.v9.87 kB2005-02-27 17:26
Sim_Behav.bat274.00 B2006-11-14 19:19
timescale.v22.00 B2006-11-14 19:33
transcript2.29 kB2006-11-28 21:23
tst_bench_top.v14.77 kB2006-11-16 10:24
vish_stacktrace.vstf6.94 kB2006-11-16 10:01
vsim.wlf80.00 kB2006-11-16 10:29
wb_master_model.v5.50 kB2006-11-10 09:47
01.96 kB
01.96 kB
verilog.asm34.38 kB2006-11-28 21:23
_primary.dat4.29 kB2006-11-28 21:23
_primary.vhd876.00 B2006-11-28 21:23
01.96 kB
verilog.asm33.15 kB2006-11-28 21:23
_primary.dat6.85 kB2006-11-28 21:23
_primary.vhd1.62 kB2006-11-28 21:23
01.96 kB
verilog.asm23.21 kB2006-11-28 21:23
_primary.dat4.04 kB2006-11-28 21:23
_primary.vhd1.35 kB2006-11-28 21:23
01.96 kB
verilog.asm26.03 kB2006-11-28 21:23
_primary.dat3.83 kB2006-11-28 21:23
_primary.vhd951.00 B2006-11-28 21:23
01.96 kB
verilog.asm4.53 kB2006-11-28 21:23
_primary.dat522.00 B2006-11-28 21:23
_primary.vhd401.00 B2006-11-28 21:23
01.96 kB
verilog.asm121.32 kB2006-11-28 21:23
_primary.dat7.65 kB2006-11-28 21:23
_primary.vhd627.00 B2006-11-28 21:23
01.96 kB
verilog.asm27.79 kB2006-11-28 21:23
_primary.dat2.34 kB2006-11-28 21:23
_primary.vhd751.00 B2006-11-28 21:23
_info1.69 kB2006-11-28 21:23
<syntmp.msg>0.00 B2006-11-07 21:22
test.prd260.00 B2006-11-12 21:09
test.prj1.27 kB2006-11-12 21:09
I2C26.00 kB2006-11-16 10:30
[#U539f#U521b]#U517c#U5bb9opencores_org#U7684I2C335.64 kB2008-12-30 13:43
...
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Comments

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1618091908
2017-02-24

不错

vhaditya
2017-08-05

mem_updatwe

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I2C Slave AND I2C Master (321.72 kB)

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