Home » Source Code » H264 IP core written in Verilog

H264 IP core written in Verilog

Peilong
2013-11-25 02:58:04
The author
View(s):
Download(s): 8
Point (s): 3 
Category Category:
verilogverilog VHDLVHDL

Description

A well-written H.264/AVC Baseline Decoder IP core.

Usage instructions can be found under directory : trunk/doc/nova_spec.doc

Also contains testbench file.

Extremmely easy to understand.

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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
01.97 kB
01.97 kB
01.97 kB
01.97 kB
01.97 kB
01.97 kB
readme.txt16.00 B2008-04-29 22:58
01.97 kB
readme.txt16.00 B2008-04-29 22:58
01.97 kB
Beha_BitStream_ram.v1.16 kB2008-04-29 22:58
BitStream_buffer.v11.65 kB2008-04-29 22:58
BitStream_controller.v25.60 kB2008-04-29 22:58
bitstream_gclk_gen.v12.67 kB2008-04-29 22:58
BitStream_parser_FSM_gating.v27.58 kB2008-04-29 22:58
bs_decoding.v45.34 kB2008-04-29 22:58
cavlc_consumed_bits_decoding.v1.85 kB2008-04-29 22:58
cavlc_decoder.v10.33 kB2008-04-29 22:58
CodedBlockPattern_decoding.v5.83 kB2008-04-29 22:58
dependent_variable_decoding.v2.42 kB2008-04-29 22:58
DF_mem_ctrl.v29.69 kB2008-04-29 22:58
DF_pipeline.v33.65 kB2008-04-29 22:58
DF_reg_ctrl.v15.94 kB2008-04-29 22:58
DF_top.v7.41 kB2008-04-29 22:58
end_of_blk_decoding.v2.82 kB2008-04-29 22:58
exp_golomb_decoding.v6.17 kB2008-04-29 22:58
ext_frame_RAM0_wrapper.v5.09 kB2008-04-29 22:58
ext_frame_RAM1_wrapper.v5.10 kB2008-04-29 22:58
ext_RAM_ctrl.v3.46 kB2008-04-29 22:58
heading_one_detector.v2.51 kB2008-04-29 22:58
hybrid_pipeline_ctrl.v10.79 kB2008-04-29 22:58
Inter_mv_decoding.v93.25 kB2008-04-29 22:58
Inter_pred_CPE.v3.74 kB2008-04-29 22:58
Inter_pred_LPE.v23.87 kB2008-04-29 22:58
Inter_pred_pipeline.v33.29 kB2008-04-29 22:58
Inter_pred_reg_ctrl.v124.27 kB2008-04-29 22:58
Inter_pred_sliding_window.v130.18 kB2008-04-29 22:58
Inter_pred_top.v28.66 kB2008-04-29 22:58
Intra4x4_PredMode_decoding.v14.99 kB2008-04-29 22:58
Intra_pred_PE.v69.16 kB2008-04-29 22:58
Intra_pred_pipeline.v32.46 kB2008-04-29 22:58
Intra_pred_reg_ctrl.v36.37 kB2008-04-29 22:58
Intra_pred_top.v14.40 kB2008-04-29 22:58
IQIT.v32.48 kB2008-04-29 22:58
level_decoding.v7.45 kB2008-04-29 22:58
nC_decoding.v30.47 kB2008-04-29 22:58
nova.v8.19 kB2008-04-29 22:58
nova_defines.v12.10 kB2008-04-29 22:58
nova_tb.v2.92 kB2008-04-29 22:58
NumCoeffTrailingOnes_decoding.v25.79 kB2008-04-29 22:58
pc_decoding.v10.34 kB2008-04-29 22:58
QP_decoding.v2.31 kB2008-04-29 22:58
ram_async_1r_sync_1w.v2.71 kB2008-04-29 22:58
ram_sync_1r_sync_1w.v3.01 kB2008-04-29 22:58
reconstruction.v22.49 kB2008-04-29 22:58
rec_DF_RAM0_96x32.v18.23 kB2008-04-29 22:58
rec_DF_RAM0_wrapper.v1.73 kB2008-04-29 22:58
rec_DF_RAM1_96x32.v18.23 kB2008-04-29 22:58
rec_DF_RAM1_wrapper.v1.73 kB2008-04-29 22:58
rec_DF_RAM_ctrl.v6.42 kB2008-04-29 22:58
rec_gclk_gen.v16.68 kB2008-04-29 22:58
run_decoding.v11.61 kB2008-04-29 22:58
sum.v23.78 kB2008-04-29 22:58
syntax_decoding.v24.94 kB2008-04-29 22:58
timescale.v546.00 B2008-04-29 22:58
total_zeros_decoding.v14.96 kB2008-04-29 22:58
01.97 kB
readme.txt16.00 B2008-04-29 22:58
01.97 kB
01.97 kB
nova_spec.doc3.09 MB2008-05-02 01:17
readme.txt43.00 B2008-05-02 01:29
01.97 kB
readme.txt16.00 B2008-04-29 22:58
01.97 kB
Beha_BitStream_ram.v1.16 kB2008-04-29 22:58
BitStream_buffer.v11.65 kB2008-04-29 22:58
BitStream_controller.v25.60 kB2008-04-29 22:58
bitstream_gclk_gen.v12.67 kB2008-04-29 22:58
BitStream_parser_FSM_gating.v27.58 kB2008-04-29 22:58
bs_decoding.v45.34 kB2008-04-29 22:58
cavlc_consumed_bits_decoding.v1.85 kB2008-04-29 22:58
cavlc_decoder.v10.33 kB2008-04-29 22:58
CodedBlockPattern_decoding.v5.83 kB2008-04-29 22:58
dependent_variable_decoding.v2.42 kB2008-04-29 22:58
DF_mem_ctrl.v29.69 kB2009-02-10 02:28
DF_pipeline.v33.65 kB2009-02-10 02:28
DF_reg_ctrl.v15.94 kB2009-02-10 02:28
DF_top.v7.41 kB2009-02-10 02:28
end_of_blk_decoding.v2.82 kB2008-04-29 22:58
exp_golomb_decoding.v6.17 kB2008-04-29 22:58
ext_frame_RAM0_wrapper.v5.09 kB2008-04-29 22:58
ext_frame_RAM1_wrapper.v5.10 kB2008-04-29 22:58
ext_RAM_ctrl.v3.46 kB2008-04-29 22:58
heading_one_detector.v2.51 kB2008-04-29 22:58
hybrid_pipeline_ctrl.v10.79 kB2008-04-29 22:58
Inter_mv_decoding.v93.25 kB2009-02-10 02:28
Inter_pred_CPE.v3.74 kB2009-02-10 02:28
Inter_pred_LPE.v23.87 kB2009-02-10 02:28
Inter_pred_pipeline.v33.29 kB2009-02-10 02:28
Inter_pred_reg_ctrl.v124.27 kB2009-02-10 02:28
Inter_pred_sliding_window.v130.18 kB2009-02-10 02:28
Inter_pred_top.v28.66 kB2009-02-10 02:28
Intra4x4_PredMode_decoding.v14.99 kB2008-04-29 22:58
Intra_pred_PE.v69.16 kB2008-04-29 22:58
Intra_pred_pipeline.v32.46 kB2008-04-29 22:58
Intra_pred_reg_ctrl.v36.37 kB2008-04-29 22:58
Intra_pred_top.v14.40 kB2008-04-29 22:58
IQIT.v32.48 kB2008-04-29 22:58
level_decoding.v7.45 kB2008-04-29 22:58
nC_decoding.v30.47 kB2008-04-29 22:58
nova.v8.19 kB2008-04-29 22:58
nova_defines.v12.10 kB2008-05-02 02:40
nova_tb.v2.92 kB2008-04-29 22:58
NumCoeffTrailingOnes_decoding.v25.79 kB2008-04-29 22:58
pc_decoding.v10.34 kB2008-04-29 22:58
QP_decoding.v2.31 kB2008-04-29 22:58
ram_async_1r_sync_1w.v2.71 kB2008-04-29 22:58
ram_sync_1r_sync_1w.v3.01 kB2008-04-29 22:58
reconstruction.v22.49 kB2008-04-29 22:58
rec_DF_RAM_ctrl.v6.42 kB2008-04-29 22:58
rec_gclk_gen.v16.68 kB2008-04-29 22:58
run_decoding.v11.61 kB2008-04-29 22:58
sum.v23.78 kB2008-04-29 22:58
syntax_decoding.v24.94 kB2008-04-29 22:58
timescale.v546.00 B2008-04-29 22:58
total_zeros_decoding.v14.96 kB2008-04-29 22:58
01.97 kB
bin2hex.pl626.00 B2008-05-02 01:58
01.97 kB
akiyo300_1ref.txt640.00 kB2008-05-02 02:40
hex2bin.cpp566.00 B2008-05-02 01:58
readme.txt225.00 B2008-05-02 01:58
01.97 kB
...
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Comments

(Add your comment, get 0.1 Point)
Minimum:15 words, Maximum:160 words
benbem
2015-06-01

This looks like a very interesting model. But I first need to download and try it out to know for sure.

venky2404
2016-12-29

is it proven?

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H264 IP core written in Verilog (981.98 kB)

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