Multichannel Clock and Data Recovery: A Synchronou
2016-08-23
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This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple
point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The
proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer
point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The
proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer
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