AES encryption algorithm
2016-08-23
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128 bit AES encryption algorithm can be implemented on FPGA. It is implemented by Verilog. Each module has row transformation, column obfuscation, round key plus transformation, key expansion, and pdpf format. There is a complete test program testbench. It is especially suitable for the fans of AES encryption algorithm.
verilog
算法
aes
加密
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