advanced AES
2016-08-23
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In the past few days, I have been improving the AES 128 module in various parts. The most important thing I want to improve is the SubByte related steps (password and key arrangement) of my lookup table. Using the look-up table means that I have to waste a lot of valuable block ram, I can go to other places to make better use of FPGA hardware resources. This method is very easy (making fixed array values and generating statements to read from the array), but does not actually advance as well as trying to extrude as much performance as possible from the fabric as small as possible. I need a way to generate the rjindael S-box value to fly on. General equation to calculate the forward S-box value for a given byte is the inverse byte in Galois domain, and then apply an affine transformation. After some research, I came across the magic of abstract equations anchored into the friendly terms of digital logic. The basic block diagram of all steps from the paper display to the forward S-box generator is shown below. In this paper, we decompose it into the equivalent logic of each block (minus affine transformation). Based on the solitude in the above diagram, it is obvious that the calculation of the generator equation is very intense. This makes it perfect that the integral point of S-box is the nonlinearity introduced in ciphertext. If the S-box transformation is linear, the resulting logic will be very simple. On the contrary, the S-box generation method is the entanglement of several ands that jump between large-scale XOR and eight, four and two bit operations. A good way to do this is to inverse the S-box generator with the inverse affine transform on the input rather than the standard affine transform on the output of the same core multiplication inverse calculator. This will make the anti cipher S-box generator easier when it finally gets it. From this paper with a little bit of affine transformation, research information is able to achieve a single byte of combinational circuit VHDL module, forwarding s box calculation. This module is not registered, only the input, output and combinational logic circuits are in between. Based on the synthesis results of the Spartan 3E xc3s500e FPGA, the following is shown: number of slices: 42 46560% number 4 input lower urinary tract symptoms: 74 93120% maximum combined path delay: 23.143nsthe basic circuit is quite slow, but its computational complexity is also quite small. According to the result of synthesis, there are eight levels of logic in the critical path between input and output. This is not a good circuit with one cycle architecture designed by AES 128. As a small experiment, I decided to design this module for & quot; water drop & quot; in AES 128, where I replaced the standard look-up table module. I went to another module, which simulates the existing single clock cycle, full 16 byte subbytes lookup and instantiation of 16 such circuits. I fell into the AES 128 password copy of the module and synthesized it. Results: Number: 1347 4656
vhdl
aes
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