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turbo coder

2014-05-28 01:46:39
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vhdlvhdl VHDLVHDL


The energy consumption of conventionalLUT-Log-BCJR architectures cannot be significantly reduced by simply reducingtheir clock frequency and throughput. This motivates our novel architecture ofimplementing the basis ACS circuit in the system which is specifically designedto have a minimal hardware complexity and hence a low energy consumption.
<span style="font-size:12.0pt;line-height:150%;font-family:"">We validate our architecture in thecontext of an LTE turbo decoder and demonstrate that it has an order ofmagnitude lower chip area, hence reducing the energy consumption of the state-of-the-artLUT-Log-BCJR implementation by 71%. Compared to state-of-the-art Max-Log-BCJRimplementations, our approach facilitates a 10% reduction in the overall energyconsumption of at transmission ranges above 58 m.
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File list

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Name Size Date
acs.vhd4.98 kB2013-10-06 22:38
acs_sim.do2.28 kB2013-10-07 00:38
constituent_encoder.vhd3.72 kB2013-08-19 22:03
deinterleaver.vhd2.01 kB2013-08-19 22:09
dff.vhd1.83 kB2013-08-19 22:13
ex_1164.vhd54.27 kB2013-08-19 22:14
gem_mux_gate.vhd1.57 kB2013-10-06 20:33
gen_add_gate.vhd1.57 kB2013-10-06 22:09
gen_and_gate.vhd1.51 kB2013-10-06 20:41
gen_not_gate.vhd1.52 kB2013-10-06 16:30
gen_xor_gate.vhd1.57 kB2013-10-06 16:28
interleaver.vhd1.79 kB2013-08-19 22:17
switch_in.vhd2.15 kB2013-08-19 22:21
switch_out.vhd2.08 kB2013-08-19 22:24
turbo_code.do743.00 B2013-08-19 23:21
turbo_code_wave.do5.42 kB2013-08-19 23:18
Turbo_Codes.cr.mti8.30 kB2013-10-07 00:33
turbo_decoder.vhd3.61 kB2013-10-07 00:37
turbo_encoder.vhd4.31 kB2013-08-19 22:32
turbo_encoder_tb.vhd1.98 kB2013-08-19 23:08
turbo_types.vhd7.80 kB2013-10-06 23:19
xor_gate.vhd1.66 kB2013-08-19 22:36
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