FPGA Verilog PS2 Mouse control LED
2016-08-23
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FPGA verilog PS2 mouse control LED PS2 receiver module (computer to receive, send mouse)
PS2_CLK signal generated by the PS2 device that sends data to the host mouse at the same time generates the clock, the host at the falling edge of the signal read PS2_CLK (latch) for each bit.
/ * Standard mouse has two counters keep track of displacement: X and Y displacement displacement counter counter.
** 9 can be stored in two's complement, and each has an associated counter overflow flag.
** Their content with the status of the three mouse buttons and transmitted together in the form of three-byte data packet to the mobile host.
** Displacement counter represents the displacement from the last data packet is sent to the host has the amount of displacement occurs.
** Displacement counter is a 9 complement integer 2. It's the highest level as a sign seen at the first byte in the packet displacement.
PS2_CLK signal generated by the PS2 device that sends data to the host mouse at the same time generates the clock, the host at the falling edge of the signal read PS2_CLK (latch) for each bit.
/ * Standard mouse has two counters keep track of displacement: X and Y displacement displacement counter counter.
** 9 can be stored in two's complement, and each has an associated counter overflow flag.
** Their content with the status of the three mouse buttons and transmitted together in the form of three-byte data packet to the mobile host.
** Displacement counter represents the displacement from the last data packet is sent to the host has the amount of displacement occurs.
** Displacement counter is a 9 complement integer 2. It's the highest level as a sign seen at the first byte in the packet displacement.
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