VHDL Design of 16 Radix 4 point FFT
Design and functional implementation of a 16-point pipelined FFT architecture is presented.
The architecture is based on the radix-4 algorithm.
By exploiting the regularity of the algorithm, butterfly operation and multiplier modules were designed.
The architecture adopts four butterflies, and the pipeline stage is optimized to balance the processing speed and the area.
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|rad4new.vhd||4.88 kB||11-03-14 13:23|
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