code verilog cordic core
2016-08-23
0 0 0
4.0
Other
Earn points
A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details
verilog
代码
核心
CORDIC
Related Source Codes
AXI Host Slave Function Model
0
0
no vote
Axi slave to fifo code
0
0
no vote
DMA Controller Based on AHB
0
0
no vote
Verilog implementation of ldpc code
0
0
no vote
Minimum sum decoding
0
0
no vote
No comment