vhdl code for 8*1 mux design
2016-08-23
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vhdl code for 8*1 mux design
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
Z : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
vhdl
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