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Verilog design water lights

anderson
2014-10-11 22:16:53
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verilogverilog Verilog HDLVerilog

Description

Under water lights in the Verilog language module Design. Are the clock pulses + counters +LED control
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Name Size Date
01.97 kB
Block1.bdf4.28 kB2014-09-17 19:10
01.97 kB
liu.(0).cnf.cdb2.01 kB2014-09-17 18:25
liu.(0).cnf.hdb635.00 B2014-09-17 18:25
liu.(1).cnf.cdb850.00 B2014-09-17 19:10
liu.(1).cnf.hdb539.00 B2014-09-17 19:10
liu.(2).cnf.cdb704.00 B2014-09-17 19:10
liu.(2).cnf.hdb738.00 B2014-09-17 19:10
liu.(3).cnf.cdb969.00 B2014-09-17 19:10
liu.(3).cnf.hdb508.00 B2014-09-17 19:10
liu.asm.qmsg1.93 kB2014-09-17 19:10
liu.cbx.xml85.00 B2014-09-17 19:10
liu.cmp.bpm510.00 B2014-09-17 19:10
liu.cmp.cdb14.21 kB2014-09-17 19:10
liu.cmp.ecobp28.00 B2014-09-17 19:10
liu.cmp.hdb8.24 kB2014-09-17 19:10
liu.cmp.logdb4.00 B2014-09-17 19:10
liu.cmp.rdb17.30 kB2014-09-17 19:10
liu.cmp.tdb15.14 kB2014-09-17 19:10
liu.cmp0.ddb27.65 kB2014-09-17 19:10
liu.db_info136.00 B2014-09-17 18:15
liu.eco.cdb160.00 B2014-09-17 19:14
liu.fit.qmsg17.73 kB2014-09-17 19:10
liu.hier_info1.65 kB2014-09-17 19:10
liu.hif1.96 kB2014-09-17 19:10
liu.map.bpm489.00 B2014-09-17 19:10
liu.map.cdb3.99 kB2014-09-17 19:10
liu.map.ecobp28.00 B2014-09-17 19:10
liu.map.hdb7.90 kB2014-09-17 19:10
liu.map.logdb4.00 B2014-09-17 19:10
liu.map.qmsg12.17 kB2014-09-17 19:10
liu.map_bb.cdb620.00 B2014-09-17 19:10
liu.map_bb.hdb6.40 kB2014-09-17 19:10
liu.map_bb.hdbx7.43 kB2014-09-17 19:10
liu.map_bb.logdb4.00 B2014-09-17 19:10
liu.pre_map.cdb2.88 kB2014-09-17 19:10
liu.pre_map.hdb8.01 kB2014-09-17 19:10
liu.psp3.00 B2014-09-17 19:10
liu.root_partition.cmp.atm12.56 kB2014-09-17 19:10
liu.root_partition.cmp.dfp33.00 B2014-09-17 19:10
liu.root_partition.cmp.hdbx2.75 kB2014-09-17 19:10
liu.root_partition.cmp.logdb4.00 B2014-09-17 19:10
liu.root_partition.cmp.rcf3.52 kB2014-09-17 19:10
liu.root_partition.map.atm9.71 kB2014-09-17 19:10
liu.root_partition.map.hdbx2.53 kB2014-09-17 19:10
liu.root_partition.map.info575.00 B2014-09-17 19:10
liu.rtlv.hdb8.00 kB2014-09-17 19:10
liu.rtlv_sg.cdb3.13 kB2014-09-17 19:10
liu.rtlv_sg_swap.cdb657.00 B2014-09-17 19:10
liu.sgdiff.cdb3.43 kB2014-09-17 19:10
liu.sgdiff.hdb8.12 kB2014-09-17 19:10
liu.signalprobe.cdb375.00 B2014-09-17 19:10
liu.sld_design_entry.sci153.00 B2014-09-17 19:14
liu.sld_design_entry_dsc.sci153.00 B2014-09-17 19:10
<liu.syn_hier_info>0.00 B2014-09-17 19:10
liu.tan.qmsg20.30 kB2014-09-17 19:10
liu.tis_db_list.ddb173.00 B2014-09-17 19:10
liu.tmw_info37.00 B2014-09-17 19:14
prev_cmp_liu.asm.qmsg1.93 kB2014-09-17 19:10
prev_cmp_liu.fit.qmsg20.85 kB2014-09-17 19:10
prev_cmp_liu.map.qmsg6.89 kB2014-09-17 19:10
prev_cmp_liu.qmsg50.54 kB2014-09-17 19:10
prev_cmp_liu.tan.qmsg20.65 kB2014-09-17 19:10
liu.asm.rpt8.02 kB2014-09-17 19:10
liu.bsf1.54 kB2014-09-17 18:48
liu.cdf350.00 B2014-09-17 19:14
liu.done26.00 B2014-09-17 19:10
liu.fit.rpt72.05 kB2014-09-17 19:10
liu.fit.smsg411.00 B2014-09-17 19:10
liu.fit.summary397.00 B2014-09-17 19:10
liu.flow.rpt5.85 kB2014-09-17 19:10
liu.map.rpt20.73 kB2014-09-17 19:10
liu.map.smsg124.00 B2014-09-17 19:10
liu.map.summary402.00 B2014-09-17 19:10
liu.pin20.23 kB2014-09-17 19:10
liu.pof128.18 kB2014-09-17 19:10
liu.qpf908.00 B2014-09-17 18:15
liu.qsf2.95 kB2014-09-17 19:14
liu.qws440.00 B2014-09-17 19:14
liu.sof137.21 kB2014-09-17 19:10
liu.tan.rpt64.60 kB2014-09-17 19:10
liu.tan.summary1,005.00 B2014-09-17 19:10
liu.v286.00 B2014-09-17 18:24
liu.v.bak280.00 B2014-09-17 18:22
liu2.bsf1.73 kB2014-09-17 18:47
liu2.v207.00 B2014-09-17 18:31
liu3.bsf1.57 kB2014-09-17 18:47
liu3.v383.00 B2014-09-17 18:45
liu3.v.bak382.00 B2014-09-17 18:43
...
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Comments

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saqi100
2017-03-17

well explained

esteboludo11
2017-05-25

saludos buen hombre, adios y saludos

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Verilog design water lights (262.37 kB)(262.35 kB)

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