fifo path rtl design and property
2016-08-23
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Mini Design Describe
4 to 1 buffered multiplexer with arbitration and FIFO bypass This design is a buffered 4 to 1 data packet multiplexerwith arbitration and FIFO bypass. It receives data on 4 input ports and sendsdata out on 1 output port. Each of the 4 input paths is modeled as pathelements which are able to buffer data in FIFOs with a bypass for high speedtransmission. The data width of the ports and the depth of the FIFO areparameterizable. An Arbiter takes care of allowing only one input at a time totransmit data to the output port. For configuration purposes there is a simplemicroprocessor interface, which allows reading from and writing to aconfiguration and status register. Additionally it notifies the controller oferror conditions via the interrupt signal.
4 to 1 buffered multiplexer with arbitration and FIFO bypass This design is a buffered 4 to 1 data packet multiplexerwith arbitration and FIFO bypass. It receives data on 4 input ports and sendsdata out on 1 output port. Each of the 4 input paths is modeled as pathelements which are able to buffer data in FIFOs with a bypass for high speedtransmission. The data width of the ports and the depth of the FIFO areparameterizable. An Arbiter takes care of allowing only one input at a time totransmit data to the output port. For configuration purposes there is a simplemicroprocessor interface, which allows reading from and writing to aconfiguration and status register. Additionally it notifies the controller oferror conditions via the interrupt signal.
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