fulladder, 4bit adder, 74163
2016-08-23
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module fulladder(sum, c_out, a, b,c_in);
output sum;
output c_out;
input a, b;
input c_in;
wire s1,s2,c1;
xor(s1,a,b);
and(c1,a,b);
xor(sum, s1, c_in);
and(s2, s1, c_in);
xor(c_out, s2, c1);
output sum;
output c_out;
input a, b;
input c_in;
wire s1,s2,c1;
xor(s1,a,b);
and(c1,a,b);
xor(sum, s1, c_in);
and(s2, s1, c_in);
xor(c_out, s2, c1);
endmodule
module fulladder4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a;
input [3:0] b;
input c_in;
wire c1,c2,c3;
fulladder fa0(sum[0], c1, a[0], b[0], c_in);
fulladder fa1(sum[1], c2, a[1], b[1], c1);
fulladder fa2(sum[2], c3, a[2], b[2], c2);
fulladder fa3(sum[3], c_out, a[3], b[3], c3);
endmodule
module tb_fulladder4();
verilog
fulladder
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