1K SRAM seperate read and write ports, verilog cod
2016-08-23
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1K SRAM, arranged as words of 32 bit, seperate read and write ports, verilog code for ASIC design
using even parity on count of 1's.
also comes with testbench
vhdl
verilog
代码
ASIC
端口
设计
读写
独立
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