vhdl project code 2
2016-08-23
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entity bigcircuit is
Port ( left : in STD_LOGIC; --ifleft='1' then left else right
logical : in STD_LOGIC; -- iflogical='1' then logical else arithmatic
shift : in STD_LOGIC_VECTOR (2downto 0);
input : in STD_LOGIC_VECTOR (7downto 0);
output : in STD_LOGIC_VECTOR (7downto 0));
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