network on chip
2016-08-23
1 0 0
no vote
Other
Earn points
Design deals with minimizing the router port from five port to three port so that we can save power and area.
verilog
网络
芯片
Related Source Codes
AXI Host Slave Function Model
0
0
no vote
Axi slave to fifo code
0
0
no vote
DMA Controller Based on AHB
0
0
no vote
Verilog implementation of ldpc code
0
0
no vote
Minimum sum decoding
0
0
no vote
No comment