FPGA_UART_FIFO
2016-08-23
6 0 0
4.3
Other
Earn points
FPGA and PC serial communication using FIFO as a data cache. Data is read from the serial port into read cache rdfifo and controlled by the control module will write data into the cache in wrfifo, serial TX port issued a request to read data to WRFIFO and read the data.
verilog
Related Source Codes
AXI Host Slave Function Model
0
0
no vote
Axi slave to fifo code
0
0
no vote
DMA Controller Based on AHB
0
0
no vote
Verilog implementation of ldpc code
0
0
no vote
Minimum sum decoding
0
0
no vote
No comment