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Traffic light controller FPGA

冬冬luch
2015-05-05 23:03:14
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VHDLVHDL Verilog HDLVerilog

Description

1. design an intersection traffic signal timing control circuit. Requires the red and green light according to a certain rule and destroyed, and bright lights during the countdown, and running time led/LCD display.
2. when the light turned green, for the lanes to allow traffic signal lights, the lane is closed to traffic signals. Request main road passage at a time for 99 seconds, main road passage time is 30 seconds at a time. Before every transform running lanes for the green light flashes, the duration is 5 seconds. Converts a driveway up to the main road road, main road in opening hours for only 5 seconds, blinking green light shows that road is still the red light, so that has been parking cars on the main road to pass, no stop line car stops traffic. Similarly, when a lane-supported roads into main road, main road green light flashes for 5 seconds, main street is still the red light.
3. the red and green running time would be convenient to be able to reset it.
4. the devices are in-system programming and experiments.
5. describe design in VHDL language, design a test plan, by ISE design simulations. And can be downloaded to the experiment successfully on the Board.

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jiaotongdeng.docx19.99 kB2015-05-06 10:58
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Traffic light controller FPGA (17.33 kB)

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