3 router design and verification
2016-08-23
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Application background
This is the source code of a Router digital system used inside the Ethernet.The code has been written in Verilog using behavioral model.
there are 3 slave and one master , thats why it is called 1x3 configuration.
Key Technology
The main RTL has been made using Xilinx ISE simulator.FPGA implementation has been done on sparten family FPGA.
Alhou, ASIC implementation could also be done using any standard tool like Synopses etc.
vb
路由器
设计
验证
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