An effective high throughput FPGA AES multi Gigabi
2016-08-23
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Application background
In this paper, we have presented an efficient nonpipelinedimplementation of AES-128 to achieve high
throughput so that it can be used in gigabit protocols. We
have implemented our design of AES-128 encryption and
decryption on a Xilinx Virtex-7 FPGA and achieved
throughput of 5.30/ 4.86 Gbps in ECB mode and 5.23/4.84
Gbps in CBC mode.
Key Technology
Due to the requirement of high throughputarchitecture for encrypted channels, an efficient
implementation of hardware is needed. This can be achieved
by using smart utilization of high end reconfigurable
platforms. To achieve convincingly high throughput, an
efficient non-pipelined style implementation of Advanced
Encryption Standard (AES) with key size of 128-bit, for multigigabit
protocols on Field Programmable Gate Array (FPGA)
is presented.
vhdl
fpga
aes
协议
一个
实现
吞吐量
有效
千兆
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