SPI implementation of the Verilog interface clock
2016-08-23
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SPI interface to achieve the clock frequency and synchronization, master SPI and slave to achieve the synchronous communication.In the main device side of the configuration SPI interface clock must be clear from the device's clock requirements, because the main device side of the clock polarity and phase are from the device as the benchmark The SPI bus has four working modes, which is most widely used is SPI0 and SPI3 (solid line);In SPI operation, the most important two settings are clock polarity (CPOL or UCCKPL) and clock phase (CPHA or UCCKPH). The clock polarity is set to the level of idle time, the clock phase is set to read data and send data to the clock edge.The host and the transmitting data from the computer are completed simultaneously, both of the receiving data is also completed. Therefore, in order to guarantee the correct communication between master and slave, the SPI has the same clock polarity and clock phase.verilog
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