Project for University of Utah ECE6710 Team 10 Fall 2007
2016-05-20
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Welcome to ECE6710 Team 10's Project webpage!
We are a group of engineers from the University of Utah working on our class project for VLSI Design. The project will be an implementation of CR16 in VHDL & Verilog using the Cadence suite of tools.
Please check first the Meeting Notes page where Eli will be posting meeting notes from each meeting to facilitate communication.
Also make sure to spend some time looking at the Recent Issues page and the Current Assignments
Eli is currently working on cleaning up matt's cadence-f07 directory since we have totally destroyed it with our project. In order to do so, he has created the Project Directory Key page which houses information
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