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verilog 多周期CPU设计

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2017-02-19 05:54:35
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Description

计算机组成与设计课程设计

用verilog与FPGA设计多周期CPU

通过modelsim仿真与ISE综合

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File list

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Name Size Date
add_32bits.v847.00 B2015-01-19 00:05
add_4bits.v683.00 B2015-01-19 00:06
add_4bits_select.v562.00 B2015-01-19 00:07
ALU.v3.92 kB2015-01-19 00:34
ALUControl.v4.07 kB2015-01-19 19:05
ALUControl.v.bak4.19 kB2015-01-19 00:42
ALU_tb.v2.89 kB2014-11-24 16:26
BLKMEMDP_V6_3.v48.82 kB2013-10-14 02:39
cunit.v8.70 kB2015-01-19 00:50
cunit_tb.v2.07 kB2014-11-24 16:26
D_32bits.v171.00 B2015-01-19 00:10
D_32bits_reset.v392.00 B2015-01-19 15:25
eunit.v2.41 kB2016-12-07 18:26
eunit.v.bak2.53 kB2016-11-28 17:43
iunit.v1.15 kB2015-01-19 20:01
Memory.v4.73 kB2014-11-24 16:26
mips_cpu_top.v2.14 kB2015-01-19 20:04
mips_cpu_top.v.bak2.25 kB2015-01-19 00:18
munit.v1.25 kB2015-01-19 18:02
munit.v.bak1.24 kB2015-01-19 17:51
Registers.v1.44 kB2015-01-19 00:30
ROM_array.v754.00 B2015-01-19 20:02
top_tb.v1.22 kB2014-11-24 16:26
src0.00 B2016-12-07 18:30
...
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verilog 多周期CPU设计 (25.28 kB)

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