Six way responder based on FPGA
2018-05-23
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The specific requirements are as follows: 1) digital intelligent responder which can accommodate six groups of contestants, each group has a responder button for responders; 2) the circuit has the identification and latch function of the first responder signal; 3) scoring circuit; 4) foul circuit. The top-level design is built by connecting graphic modules, and the top-level functional modules are written in VHDL language
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