Frequency division and name output
2018-05-17
1 0 0
no vote
Other
Earn points
Divide the 50 MHz clock resource, output 128 kHz clock signal, store the ASCII code of the name in the array, and output 128 kHz clock signal The frequency division principle of Z output per clock is as follows: the frequency division factor is 194h, the counter counts from 0, and the rising edge of CLK is valid. When the counter accumulates to 194h, half of the cycle of clk128 has been completed. At this time, clk128 is turned over, and then the frequency division factor is cleared. At the end of 1 / 2 cycle, the counter starts counting again until the next turn.
Related Source Codes
Android AOA Android Open Accessory Development Usi
0
0
no vote
Golang AOA Android Open Accessory HID Control
0
0
no vote
PClite
0
0
no vote
GMSK Linear Receiver
0
0
no vote
The golden version of AFT that has been passed dow
0
0
no vote
No comment