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Study on Turbo Code decoder and FPGA implementation.

Altera Quartus II software platform completed the decoding of Turbo codes based on Log-MAP algorithm for FPGA design and implementation. In Turbo yards of FPGA design and achieved part, main for has Turbo yards of compiled yards device in the all important module for has design and achieved, such as...

VHDL realization of 3*3 matrix multiplication

Matrix multiplication vhdl implementation, dimension fixed, very instructive.Focus on understanding the interface, timing settings, delay control. Because the structure is relatively clear, not added stimulus file, you can write your own....

verilog code for uart transmission

the low power low cost data transmission teq done by UART chech it once it's writen in verilog language and also it's a protocol based where you are going to specify your own rules for better communication...

high speed ADC-ADC08D1000 comunication in FPGA

This is a program developed by Arron lee, in order to control ADC08D1000 Analog-to-digital device in FPGA, Xilinx Virtex-4 SX35 FPGA is applied here, the DCM is used to control the clock path in FPGA, the clock source is AD9517 which controled by serial port in FPGA...

FPGA source audio signal Analyzer

Audio signal through consists of the OPAMP and the resistance of the 50Ohm impedance matching circuit to meet the input impedance 50 Ohm system requirements, calculation of signal power. In order to ensure that this signal is undistorted sampled signals through the cut-off frequency for the 10Khz an...

Discrete Cosine Transform(DCT/IDCT) in VHDL

the Project aim is to design DCT and IDCT in VHDL. DCT is used in image compression to compress the JPEG image. This file contains DCT and IDCT blocks and top module which integrates two blocks and testbench to test the two modules....

VHDL4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...

VHDL-based design and analysis of digital clock

Digital Clock is a digital circuit implementation, minutes, seconds, timing devices, compared with the mechanical clock has a higher accuracy and intuitive, and no mechanical devices, with longer life, so it has been widely use. In principle figure is a typical digital circuit, including combination...

VHDL Design of 16 Radix 4 point FFT

Design and functional implementation of a 16-point pipelined FFT architecture is presented.  The architecture is based on the radix-4 algorithm.  By exploiting the regularity of the algorithm, butterfly operation and multiplier modules were designed.  The architect...

VHDL 100 examples

Share online for some 100 examples suitable for FPGA learning for beginners. Inside there are some classic tricks....

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