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circular FIFO buffer

This is a simple circular fist-in first-out queue in vhdl. The buffer size and data size can be configured through N and W parameters. The head of queue is available on output data. Two signals control the write and read of data. Two output signals info if buffer is empty or full....

LED测试小程序

可实现任意频率的LED点灯形式,只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式,只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式,只需改变分频次数和赋值就...

七分频数字电路—VHDL

本程序描述了七分频数字电路,程序经过仿真,可以使用。该程序的设计方法为常用的奇数分频设计方法,简单易懂,具体方法描述网上很多,此外设计其他类似的奇数分频电路时,可以直接改动程序中相应的参数即可。文件中...

AND2 VHDL 代码

此程序描述了数字电路中与门的逻辑功能。所采取的硬件描述语言为VHDL。程序结构采用了dataflow的写法。请大家仔细阅读。本程序已通过了Altera quartus的验证。确保准确无误。...

d ,t flip flop

the program is vhdl code on d , t , jk flip flop along with test bench...

Servo Motor

in this brief code we generate a pulse from PWM with VHDL....

八位数码管动态显示

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;--------------------------------------------------------------------entity seg_display is  port( clk    :  in   std_logic;       ...

北邮数电实验代码

实验一:QuartusⅡ原理图输入法设计与实现一:实验要求    ①:用逻辑门设计实现一个半加器,仿真验证其功能,并生成新         的半加器图形模块单元。    ②:用实...

基于FPGA的数字频率计VHDL源码(精确到1.1hz至20.0mhz)

当时是用于课程设计而编写的代码,经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码(精确到1.1hz至20.0mhz)...

VHDL语言串口接收数据

VHDL语言,实现穿行数据接收的功能,将异步串口的数据转换为八位数据存储。...


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