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circular FIFO buffer

This is a simple circular fist-in first-out queue in vhdl. The buffer size and data size can be configured through N and W parameters. The head of queue is available on output data. Two signals control the write and read of data. Two output signals info if buffer is empty or full....

七分频数字电路—VHDL

本程序描述了七分频数字电路,程序经过仿真,可以使用。该程序的设计方法为常用的奇数分频设计方法,简单易懂,具体方法描述网上很多,此外设计其他类似的奇数分频电路时,可以直接改动程序中相应的参数即可。文件中...

AND2 VHDL 代码

此程序描述了数字电路中与门的逻辑功能。所采取的硬件描述语言为VHDL。程序结构采用了dataflow的写法。请大家仔细阅读。本程序已通过了Altera quartus的验证。确保准确无误。...

Servo Motor

in this brief code we generate a pulse from PWM with VHDL....


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