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VGA display based on FPGA

Implementation of FPGA-based VGA display, measurements compiled too, different version should be changed accordingly (PS: don't know much about)...

VHDL breathing lamp procedures, VHDL learning routines

This code is absolutely true and reliable, FPGA breath lamp written in VHDL language. You can refer to the study, for the VHDL entry is very helpful. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; has passed through the compiler, has realize...

HDB3 encoder

Based on FPGA as a hardware platform, QUARTUS II software platform based on EDA tools to achieve the HDB3 encoder/decoder. Because on the QUARTUS II EDA software platform cannot handle bipolar signals, and HDB3 encoder/decoder implementations include: software and hardware components. Piece is based...



LS OFDM channel estimation algorithm for FPGA realization

This program is used to implement hardware emulation LS OFDM channel estimation algorithm, written in FPGA-based development of VHDL, the simulation waveforms of each module, for your reference exchange....

The implementation of Hdb3 encoding based on FPGA

HDB3 code is a bipolar NRZ based on the improvement of the AMI code, not only does it have no DC component in the power spectrum, like the AMI code, and can be self-test error, etc., but also overcomes the time extraction difficulty when there is continuous "0" appears in the AMI...

FPGA drive a single lamp form dot matrix program

The program set up FPGA 5x5 dot matrix driver, the code is relatively simple, this program can be used as a FPGA output control, driving voltage stabilizing chip,and lighting...

spartan 3 VHDL time set and reverse counter with BCD

The spartan3 Starter Kit board is used to set time and Count down to 0.Each Digit is available to set by push button next_d. The value is able to change by button plus or minus.Switch 'start' is used to Count down the or set the time.The Display Shows hours and mins or Switch stt is 'on' it Sho...

High speed ADC control

Build environment for windows - xp; ISE12.4; using xilinx's V6 series FPGA control a high-speed AD ---- AD5463, this ADC is 12, the maximum sampling rate of up to 500MSPS, and configuration and wiring is simple, has a wide range of uses in the intermediate frequency radar signal processor.The source...

SDRAM Controller with Arbiter

SDRAM Controller for multi-CPU system with an arbiter which will schedule the memory access....

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