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FPGA stepper motors

Stepping Motor based on FPGA design of stepping motor controller based on FPGA in the analysis on the basis of the principle of stepping motor,Hierarchical design with VHDL program is given, and use the Quartus II simulation and simulation results are presented. It with the FPGA core devices, greatl...

Elevator system based on VHDL

Application backgroundBased on VHDL to realize the movement of four floors elevator, realize the normal operation of the elevatorKey TechnologyVHDL, state machine, compiler, trigger, comparator....

Aes_pipeline

Application backgroundThe pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm.The inputs to the overall processor are as follows:  clk i: System Clock, Data I/O at rising edge  rst i: Asynchronous Reset, active high, initializes all input...

Xmatchpro lossless compression

Application backgroundThe Lossless data compression system is a derivative of the XMatchPro Algorithm which  originates  from  previous  research  of  the  authors  and  advances  in  FPGA technology. The flexibility provided by using this tec...

FPGA core AES-GCM core 100G Ethernet Application

Application backgroundIn this paper we have presented an efficient design methodology to implement in reconfigurable hardware devices the GCM combined with the AES for authenticated encryption. Thanks to the replication of four AES cores and four binaryfield multipliers we were able to demonstra...

Improve the throughput of Karatsuba AES-GCM FPGA of the pipeline multiplier

Application backgroundIn this paper, we presented the throughput improvement of AES-GCM with pipelined Karatsuab-Ofman based finite field multipliers.With our proposed 4-stage sub-quadratic finite field multipliers, the GHASH function is not the bottleneck any more in GCM hardware systems, no mat...

FIR filter graduation design

Application backgroundFir (finite impulse response) filter: finite length unit impulse response filter, also known as non recursive filter is the most basic components of digital signal processing system, which can guarantee any amplitude frequency characteristics at the same time has strict linear...

Orthogonal Latin Square algorithm for fault detection

An error correcting and single stuck at fault detection code using orthogonal latin square is written in vhdl. The code can correct error upto 3 errors. The fault in syndrome generator error pattern calculator and roth1 generator can be detected using this code. Simultaneously the error is cor...

Flash NAND controller VHDL code

The information is based on the NAND flash FPGA controller research, language is VHDL, the code has been verified by simulation...

svpwm

SVPWM pulse generation. VHDL code for Induction Motor...

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