Sort by
  1. Language:All
  2. Category:vhdl
  3. Time:ALL
  4. View:1000 times
Remove all
Language More Hide
Category More Hide
Time
View
More

reconfigurable fir filter vhdl code

this is an fir filter implementation code for a reconfigurable fir filter design coded in vhdl language...

VHDL for 16 bit Time Domain Convolution

Convolution is a common operation in digital signal processing. In this project, I created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism to improve performance compared to a microprocessor. Convolution takes as input a signal and a kernell The...

VHDL simulation of direct sequence spread spectrum communication system

Direct sequence spread spectrum communication system : Contains: 信源 、 扰码 、 交织 、 直扩 、 BPSK 调制、 解调 、 相关 、 Interwoven solutions for 、 解扰 Several parts through QuartusII 9 compiler testing is feasible. Code original containing syste...

Micron Nand Flash controller

The controller micron companies, it is a reference nature, with the flash of shoes can download the reference,  containing ECC function...

16/64 point FFT

This is a FFT library function by using VHDL code. It can switch the length of FFT between 16 point and 64 point. It contains the butterfly, twiddle factor, ROM, RAM and so on. And it can successfully run on Quartus 2 or other software....

OFDM Modulation and Demodulation

Cyclic prefix insertion is commonly used in orthogonal frequency division multiplexing (OFDM) systems as a way  to mitigate the effects of intersymbol-interference (ISI). It copies the end section of an inverse fast Fourier  transform (IFFT) packet to the beginning of an OFDM s...

VHDL realization of 3*3 matrix multiplication

Matrix multiplication vhdl implementation, dimension fixed, very instructive.Focus on understanding the interface, timing settings, delay control. Because the structure is relatively clear, not added stimulus file, you can write your own....

verilog code for uart transmission

the low power low cost data transmission teq done by UART chech it once it's writen in verilog language and also it's a protocol based where you are going to specify your own rules for better communication...

VHDL4 buzzer

4 people for answering system, time of 20 seconds, 20 seconds no one answer is deemed no one answering. Before you start answering as a violation vie, violation vie warns players. If there is one person answering the other 3 locks, can no longer answer. aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa...


LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D