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VGA display based on FPGA

Implementation of FPGA-based VGA display, measurements compiled too, different version should be changed accordingly (PS: don't know much about)...

The implementation of Hdb3 encoding based on FPGA

HDB3 code is a bipolar NRZ based on the improvement of the AMI code, not only does it have no DC component in the power spectrum, like the AMI code, and can be self-test error, etc., but also overcomes the time extraction difficulty when there is continuous "0" appears in the AMI...

spartan 3 VHDL time set and reverse counter with BCD

The spartan3 Starter Kit board is used to set time and Count down to 0.Each Digit is available to set by push button next_d. The value is able to change by button plus or minus.Switch 'start' is used to Count down the or set the time.The Display Shows hours and mins or Switch stt is 'on' it Sho...

High speed ADC control

Build environment for windows - xp; ISE12.4; using xilinx's V6 series FPGA control a high-speed AD ---- AD5463, this ADC is 12, the maximum sampling rate of up to 500MSPS, and configuration and wiring is simple, has a wide range of uses in the intermediate frequency radar signal processor.The source...

Maze of VHDL in digital circuit

This is an FPGA-based control panel display dot class fun little puzzle game where the player through the keypad ↑ ↓ ← → keys to control the control characters move around, from the starting point of view, the purpose of exports went to the maze. The game has a user-friendly interface, and t...

vhdl code for counter

using this  code we develop counter program of plc in fpga hardware...

Frequency generator based on FPGA

The program mainly for Altera, Xilinx FPGA series controlled frequency generator design, details of the program as described in the program notes section, program annotations in each part of the process....

FPGA implementation of dct1d core

Application background In order to achieve good compression performance, correlation between the color components is first reduced by converting the RGB color space into a decorrelated color space. In baseline JPEG, a RGB image is first transformed into a luminance-chrominancc color space such...

Elevator system based on VHDL

Application backgroundBased on VHDL to realize the movement of four floors elevator, realize the normal operation of the elevatorKey TechnologyVHDL, state machine, compiler, trigger, comparator....

Aes_pipeline

Application backgroundThe pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm.The inputs to the overall processor are as follows:  clk i: System Clock, Data I/O at rising edge  rst i: Asynchronous Reset, active high, initializes all input...

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