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AXI slave verilog code

Wrote AXI slaver Verilog code, hope to give you some inspiration...

Verilog Jpeg Encoder

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bit stream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

DDR2 controller, Verilog source code

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...

Flash controller verilog code

This is the verilog code of Samsung K9 series Flash controller, it is complied and verified on FPGA development board, the verification environment is quartusii and modelsim combined platform. You can find the datasheet of K9 flash on the internet. The size of the flash is 1024*32....

1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

I2C Slave AND I2C Master

I2C Slave is inside and the I2C Master and contain the emulator as well as wave files, I took a look at, particularly easy to understand...

Histogram equalization FPGA implementation

Real-time image histogram equalization in FPGA, effective use of FPGA chip-chip resources, no need to add external memory chips. The code is based on YCbCr, actually only the luminance histogram equalization, time after which a synchronous CB,CR color components, avoiding partial color problem! Code...

Cache memory

This code is the code cache, using the least recently used algorithm. Roughly 1000-2000 lines of code, the program includes cache replacement algorithm implementations. Selection of image rules, as well as all of the simulations....

FFT FFT algorithm based on Verilog

This code implements 128 points, FFT calculation of 16-bit integers, Quartus II version 8.0, as verified by simulation, timing constraints and practical verification program features can fully meet demand under normal circumstances, clocking 150Mhz....

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