Sort by
  1. Language:All
  2. Category:verilog
  3. Time:ALL
  4. View:All
Remove all
Language More Hide
Category More Hide
Time
View
More

I2C IP core and testbench

I2C IP core with the testbench, written in Verilog, including master,slave reg...

Verilog implementation of cordic algorithm

CORDIC algorithm can be implemented through different forms of solving multiplication, Division, square root, and some  trigonometric functions Operational problems. These calculation of trigonometric functions is to use hardware is Not easy to attain, and the CORDIC algorithm can...

SDRAM program controller

This article now video surveillance needs, designs and implements a method based on FPGA Chip's video surveillance system. The system using Verilog HDL language to describe the entire hardware architecture, makes the system more stable, operation is simple. The system through OV7670 camera to obtain...

Ov5620 used in FPGA

Ov5620 used in FPGA, the program's function is to drive the camera OV5620 and data output through the VGA interface, external monitor See the webcam image....

Driving LCD1602 FPGA code

This is the code I write the LCD1602 tested can normally run on the LCD1602 again, because my own Board is made of 4 lines, via 4-wire communications, data programming students to know 8 line, try the 4 data bits, how to program...

Traffic light verilog HDL source code

It is the source code of verilog HDL for a street light. The LED on the board represent the green, yellow and red light.After some fixed time, the LED will be on or off for the command. Besides, the time will be count backwards, and it will be shown on the screen of the  board. It is very...

Content Addressable Memory (CAM)

Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data s...

DUC digital upconversion design

Upconversion <span style = "font-size: 12.0pt; font-family:" "> DUC is the local oscillator frequency and the signal frequency sum DUC's output 0.2MHz, based oscillator and signal frequency addition, -0.2MHz for image frequency. Its main features include three aspects: first, co...

UVM MEMORY WORKING EXAMPLE

HI FOLKS,THE ATTACHED FILE CONTAINS THE COMPLETE WORKING EXAMPLE FOR UNIVERSAL VERIFICATION METHODOLOGY BASED ON SYSTEM VERILOG...

Verilog code FIFO

FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optionalhandshake signals for interfacing with the user logic. It is often used tocontrol the flow of data between source and destination. FIFO can beclassifie...

prev 1.. 6 7 8 9 10 11 12 13 14 ... 80 next

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D