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Median filter Verilog implementation

Verilog implementation of median filtering algorithm. Can be used for digital signal processing FPGA-based embedded image processing or related. Verilog implementation of median filtering algorithm. Can be used for digital signal processing FPGA-based embedded image processing or related. Hope can h...


DE2_70_D5M_LTM mainly in the DE2-70 development of a video capture and LTM displayed on the platform process, the platform can be used as image processing and graphics hardware, the system can be improved and extended, such as video surveillance systems...

Verilog AD9910 code

Application backgroundAD9910 is a direct digital frequency synthesizer (DDS) with 14 DAC bit, which supports up to 1 GSPS of the sampling rate. AD9910 uses advanced DDS patented technology, without sacrificing the performance of the premise can greatly reduce power consumption. The high frequency an...

Black gold development board Alinx DDR2 read and write controller

Application backgroundThe project for black Alinx development board supporting the project, the realization of the real-time video acquisition and processing, code structure complete and clear, very suitable for video processing algorithms of transplantation.Key TechnologyThis project mainly complet...

IIC bus Verilog implementation (read and write 16 for the data)

Application backgroundThis code is the subject of the research in the driver of a peripheral module, in order to read and write commands in the peripheral IIC bus transmission protocol, but because of the device's command and register state to the word as the unit, the general situation of the IIC b...

SPI_slave code, has been practical!

SPI_slave code, address length can be set to 1 ~ 3 bytes, the clock can run to 20MHz or more, has been used in the project, there is a need to be modified according to their own requirements!!!!...

FPGA implementation of SVPWM Technology

FPGA implementation of SVPWM technology, SVPWM signal waveform generation, dead time control, real-time requirements and other issues.SVPWM: space vector pulse width modulation (Vector Pulse Width Modulation Space)...

Gaussian Random number generator (hardware implemented)

This is hardware implemented Gaussian random number generator based on the article attached in the folder "Document" The system is based on the Ziggurat Gaussin random algorithm and implemented when I was under-graduate. Although it is not my original system, it is so helpful cause I can acquire a...

AD chip SPI interface configuration

Generated by the FPGA simulation of SPI interface timing, complete the AD chip configuration, AD chip of ADI company ad9852, program to configure more detailed, for using similar AD chip developer reference...

FPGA reference design AD9267

High speed ADC AD9267 10bit FPGA reference design Verilog language Contains a Xilinx ISE12.2 Engineering...

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