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FPU Floating point unit verilog VHDL

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method. ...

ddr3 sdram controller

This is the verilog code for DDR3 SDRAM controller. Welcome to download and use. Thank you for your support!!!...

SPI verilog source code

The Serial Peripheral Interface or SPI bus is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode. It is used for short distance, single  master communication, for example in embedded systems, sensors, and SD cards. Devices comm...

Verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

sobel edge detection

This VHDL/Verilog or C/C++ source code is intended as a design reference which illustrates how these types of functions can be implemented.  It is the user's responsibility to verify their design for consistency and functionality through the use of formal verification methods.&nb...

Verilog examples

Learn verilog Common programming methods and examples. Welcome to download and trial. Thank you all for your support!...

Four ov7670 camera image acquisition and VGA display system based on FPGA

Application backgroundApplication in multi - channel image parallel acquisition and display.Key TechnologyBased on the FPGA image processing development board completed a four way image acquisition, and send VGA sub screen display, the program is written in the Verilog hardware language, the camera...

Complete SD controller! Supported file systems.

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and...

aynchronous fifo project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...

ADPLL behavior model

The attached files contain the behavior model of ADPLL. The 6 bits TDC is used. A fast clock is used to count the the timing difference between the input reference clock and feedback clock. The TDC resolution is higher if the fast clock is faster. The digital loop filter produces 1...

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