Sort by
  1. Language:All
  2. Category:verilog
  3. Time:ALL
  4. View:All
Remove all
Language More Hide
Category More Hide
Time
View
More

Pipelined FFT/IFFT 64 points processor

64 -point radix-8 FFT.   Forward and inverse FFT.    Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.   Input data, output data, and co...

Nexys 4 digital tube display clock

On Nexys4 Development Board implements a clock display, using persistence of vision function of digital output, but due to problems of time, hour digits only designs a bit, need two plus one....

SPI Verilog implementation of detailed and comprehensive

Verilog implementation of SPI (a very comprehensive and detailed, but also with a SPI algorithm annotations), this code is the SPI interface's Master and slaver Verilog source code...

APB protocol

APB master and slave implemented in verilog. State machines of both master and slave is designed, APB mainly is used for low bandwidth peripherals. ...

FPGA DDS generators

DE2 development platform, uses the Veriolg language programming realized DDS signal output, frequency and step wave output with adjustable using Modelsim and FPGA embedded logic Analyzer verifies the correctness of design, can meet the needs of engineering....

Four ov7670 camera image acquisition and VGA display system based on FPGA

Application backgroundApplication in multi - channel image parallel acquisition and display.Key TechnologyBased on the FPGA image processing development board completed a four way image acquisition, and send VGA sub screen display, the program is written in the Verilog hardware language, the camera...

xilinx pcie verilog code

For study and research on PCIe hardware Has a complete simulation testbench and Xilinx PCIe softcore...

FPGA Gaussian Filter

This filter has been designed by Verilog HDL. The function successfully simulated on ModelSim. This filter is used in video and image processing project which reduces the salt & pepper noise....

aynchronous fifo project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...

Hammond organ/music player based on FPGA device

1, can be used directly; 2, Verilog programming; 3, 16X16 matrix keyboard keystrokes can be realized; 4, you can play music of the butterfly lovers; 5, piano; 6, you can play the history of key value; 7, digital control can display key values in real time, is also...

prev 1 2 3 4 5 6 7 8 9 10 ... 73 next

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D