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FPGA Gaussian Filter

This filter has been designed by Verilog HDL. The function successfully simulated on ModelSim. This filter is used in video and image processing project which reduces the salt & pepper noise....

ADPLL behavior model

The attached files contain the behavior model of ADPLL. The 6 bits TDC is used. A fast clock is used to count the the timing difference between the input reference clock and feedback clock. The TDC resolution is higher if the fast clock is faster. The digital loop filter produces 1...

Hammond organ/music player based on FPGA device

1, can be used directly; 2, Verilog programming; 3, 16X16 matrix keyboard keystrokes can be realized; 4, you can play music of the butterfly lovers; 5, piano; 6, you can play the history of key value; 7, digital control can display key values in real time, is also...

FPGA-based control buttons VGA display pics

Using FPGA platform, 5 images 128*128, stored in ROM, press the control to stop and start the animation;...


Axilite_axistream_bfm, with this simulation model, read and write timingcan simulate AXI bus development, user defined function IP nuclear, no longer frequent download to the FPGA development board test, does not need such as ...

AHB transfers to APB source and APB read/write verilog code

Converts AHB peripheral transfers to APB transfersThe 16-Slot APB Bridge provides an interface between the high-speed AHB domain and the low-power APB domain. The Bridge appears as a slave on AHB, whereas on APB, it is the master. Read and write transfers on the AHB are converted into...

8 bit adder verilog

hey here is a ise format code for xilinx software verilog 8 bit fixed point coding use this for example for coding with test bench...

Design module Bluetooth by verilog

The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main objective for this standard is to provide a royalty free standard for such wireless protocol. The objective of this project is to build an opensource free blueto...

ahb_slave in advanced microcontroller bus architecture

An AHB bus slave responds to transfers initiated by bus masters within the system. The slave uses a HSELx select signal from the decoder to determine when it should respond to a bus transfer. All other signals required for the transfer, such as the address and control information, will be genera...

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