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floating point adder

verilog code coded in xilinx used to add 2 floating point numbers.... and the technique used in this coding is piplining........

AHB transfers to APB source and APB read/write verilog code

Converts AHB peripheral transfers to APB transfersThe 16-Slot APB Bridge provides an interface between the high-speed AHB domain and the low-power APB domain. The Bridge appears as a slave on AHB, whereas on APB, it is the master. Read and write transfers on the AHB are converted into...

code verilog cordic core

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details...

Pipelined FFT/IFFT 64 points processor

64 -point radix-8 FFT.   Forward and inverse FFT.    Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.   Input data, output data, and co...

Nexys 4 digital tube display clock

On Nexys4 Development Board implements a clock display, using persistence of vision function of digital output, but due to problems of time, hour digits only designs a bit, need two plus one....

SPI Verilog implementation of detailed and comprehensive

Verilog implementation of SPI (a very comprehensive and detailed, but also with a SPI algorithm annotations), this code is the SPI interface's Master and slaver Verilog source code...

APB protocol

APB master and slave implemented in verilog. State machines of both master and slave is designed, APB mainly is used for low bandwidth peripherals. ...

FPGA DDS generators

DE2 development platform, uses the Veriolg language programming realized DDS signal output, frequency and step wave output with adjustable using Modelsim and FPGA embedded logic Analyzer verifies the correctness of design, can meet the needs of engineering....

xilinx pcie verilog code

For study and research on PCIe hardware Has a complete simulation testbench and Xilinx PCIe softcore...

FPGA Gaussian Filter

This filter has been designed by Verilog HDL. The function successfully simulated on ModelSim. This filter is used in video and image processing project which reduces the salt & pepper noise....

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