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FPGA Gaussian Filter

This filter has been designed by Verilog HDL. The function successfully simulated on ModelSim. This filter is used in video and image processing project which reduces the salt & pepper noise....

Asynchronous clock domain crossing fifo design

Asynchronous clock domain crossing design a FIFO fifo design is one of the most common problems encountered by ASIC designers. This article focuses on howSample design FIFO-- This is a deceptively simple but complex task. The outset, we should note, FIFO is typically used transition clock domai...

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ...


Here, we present the first available open-source 512 bit RSA core. This is an early prototype version of a full FIPS Certified 512-4096 capable RSA Crypto-core which will be on sale soon. The version provided, has not the same performance than the final product since it was a proof of concept tha...

SPI interface code

Verilog programming on SPI interface,SPI is a simple interface that allows one chip to communicate with one or more other chips....

Elliptic-curve cryptography Verilog code

Elliptical encryption algorithms (ECC) is a public key encryption system, originally proposed by Miller and Koblitz, whom in 1985, its mathematical basis is the use of rational points on elliptic curves Abel ellipse on the additive group of the computational difficulty of the discrete logarithm.Stud...

ADPLL Design and Implementation on FPGA

This paper presents the ADPLL design using Verilog and its implementation on FPGA.ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulatingVerilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper,implementation of ADPLL is described in detail....

nand flash simulation model

NAND flash chip for IC chip design verification of simulation models; include model and test platform for NAND Flash controller design or verification personnel are very helpful! In addition, attach the Micron chip documentation, see PDF attachment...

Signal generator based on FPGA

Adder32.v 32-bit AdderD_FFbe.v frequency controllerDFFAF2. V phase accumulatorROM.MIF sine wave ROMSquare.v squareTrianle.v triangle...

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