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Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ...

Floating Point Unit

This document describes the Verilog double precision floating point core, these cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic. Floating Point IP Core (Verilog) The floating point IP core is separated into 7 source files: 1. fpu_double.v...


Here, we present the first available open-source 512 bit RSA core. This is an early prototype version of a full FIPS Certified 512-4096 capable RSA Crypto-core which will be on sale soon. The version provided, has not the same performance than the final product since it was a proof of concept tha...

aynchronous fifo project

First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. The dual-clock...

Face detection system designed using verilog

Face detection is designed using verilog which is designed for the implementation on DE-2 FPGA board. This project is designed to detect the human face when the camera input detects a human....

ADPLL Design and Implementation on FPGA

This paper presents the ADPLL design using Verilog and its implementation on FPGA.ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulatingVerilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper,implementation of ADPLL is described in detail....

nand flash simulation model

NAND flash chip for IC chip design verification of simulation models; include model and test platform for NAND Flash controller design or verification personnel are very helpful! In addition, attach the Micron chip documentation, see PDF attachment...

vedic multiplier 32 bit

design of high speed 32 bit vedic multiplier using vedic mahematics.this has a very less delay than other type of multipliers....

FPGA VGA display experiments

This is an original VGA interface generation code. Is allowed to experiment in a certain size of image displayed on the computer monitor. Full realization of FPGA and PC monitors of the same letter. Code design is original....

DE1 use D5M camera on VGA

This is the Demo program to use D5M. It can input the image from the D5M camera, and putout the image to the VGA. This program is very practical on first using D5M board, we can add function that we want inthis program. It is a very basis program in D5M camera and VGA. This program can us...

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