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verilog spwm

Second-class Prize in electronic design contests, implemented in the FPGA, two-way natural sampling SPWM...

Design module Bluetooth by verilog

The Bluetooth is a standard protocol for wireless connection between devices such as cell phones, PDAs, PCs and any other device. The main objective for this standard is to provide a royalty free standard for such wireless protocol. The objective of this project is to build an opensource free blueto...

ahb_slave in advanced microcontroller bus architecture

An AHB bus slave responds to transfers initiated by bus masters within the system. The slave uses a HSELx select signal from the decoder to determine when it should respond to a bus transfer. All other signals required for the transfer, such as the address and control information, will be genera...

Design of High Performance 64 bit MAC Unit

A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper. MAC unit  performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier  and the add...

verilog uart 115200

Using serial port UART transmission module written in Verilog, sending rate to 115200, input clock for 50m for many years validation without errors...

AXI slave Verilog implementation of agreements

AXI (Advanced eXtensible Interface) is a bus protocol, which was proposed by the ARM company AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol for the most part, is a high-performance, high-bandwidth, low-latency-oriented films Internal bus 。 It addresses/separation of control and data...

VGA color display the Verilog code for Xilinx FPGA

Verilog implementation of FPGA VGA sesser stripes display code, test absolutely right, can successfully implement functionality....

USB Driver and VGA Interface for FPGA

This is source code for a USB bouncing ball and VGA driver kit for the Altera DE2-115 board. Note that it's in SystemVerilog which is 100% compatible with verilog (ie you can rename the files as .v and it still works). I'd suggest using a de2 board for compilation as that's what I'm using. a test im...

AHB interface

This is the AHB simulation suite. It contains the following files:ahb_def.v - Definition fileahbmst.v - AHB master modelahbslv.v - AHB slave modelahbarb.v - AHB arbiter modelahbdec.v - AHB decoder modeltestbench.v - Top level test bench fileahb_stimuli.v - Sample AHB stimuli fileqm_ahbmst_(test_)tas...

High efficiency LDPC code encoder FPGA development, VerilogHDL, and MATLAB simulation

Application backgroundWIMAX standard uses LDPC code as its optional channel encoding program. The WIMAX standard is the fourth global 3G standard for ITU, WCDMA, CDMA200, and TD-SCDMA in 2007. LDPC code with its excellent error correction performance has become a hot research topic in recent years....

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