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Double precision floating point core Verilog

Application backgroundIEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point u...

DDS digital signal generator

Write your own DDS generators, square wave, triangle wave, sine wave, you can also enter any Waveform files...

Asynchronous clock domain crossing fifo design

Asynchronous clock domain crossing design a FIFO fifo design is one of the most common problems encountered by ASIC designers. This article focuses on howSample design FIFO-- This is a deceptively simple but complex task. The outset, we should note, FIFO is typically used transition clock domai...

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ...

Floating Point Unit

This document describes the Verilog double precision floating point core, these cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic. Floating Point IP Core (Verilog) The floating point IP core is separated into 7 source files: 1. fpu_double.v...

Face detection system designed using verilog

Face detection is designed using verilog which is designed for the implementation on DE-2 FPGA board. This project is designed to detect the human face when the camera input detects a human....

Viterbi decoding works files

The goodies site search abroad, to share. Interior contains Verilog source code format. Has the reference value very much....

Elliptic-curve cryptography Verilog code

Elliptical encryption algorithms (ECC) is a public key encryption system, originally proposed by Miller and Koblitz, whom in 1985, its mathematical basis is the use of rational points on elliptic curves Abel ellipse on the additive group of the computational difficulty of the discrete logarithm.Stud...

ADPLL Design and Implementation on FPGA

This paper presents the ADPLL design using Verilog and its implementation on FPGA.ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulatingVerilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper,implementation of ADPLL is described in detail....

vedic multiplier 32 bit

design of high speed 32 bit vedic multiplier using vedic mahematics.this has a very less delay than other type of multipliers....

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