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FPGA_UART_FIFO

FPGA and PC serial communication using FIFO as a data cache. Data is read from the serial port into read cache rdfifo and controlled by the control module will write data into the cache in wrfifo, serial TX port issued a request to read data to WRFIFO and read the data....

AHB interface

This is the AHB simulation suite. It contains the following files:ahb_def.v - Definition fileahbmst.v - AHB master modelahbslv.v - AHB slave modelahbarb.v - AHB arbiter modelahbdec.v - AHB decoder modeltestbench.v - Top level test bench fileahb_stimuli.v - Sample AHB stimuli fileqm_ahbmst_(test_)tas...

Median filter Verilog implementation

Verilog implementation of median filtering algorithm. Can be used for digital signal processing FPGA-based embedded image processing or related. Verilog implementation of median filtering algorithm. Can be used for digital signal processing FPGA-based embedded image processing or related. Hope can h...

DE2_70_D5M_LTM

DE2_70_D5M_LTM mainly in the DE2-70 development of a video capture and LTM displayed on the platform process, the platform can be used as image processing and graphics hardware, the system can be improved and extended, such as video surveillance systems...

High efficiency LDPC code encoder FPGA development, VerilogHDL, and MATLAB simulation

Application backgroundWIMAX standard uses LDPC code as its optional channel encoding program. The WIMAX standard is the fourth global 3G standard for ITU, WCDMA, CDMA200, and TD-SCDMA in 2007. LDPC code with its excellent error correction performance has become a hot research topic in recent years....

IIC bus Verilog implementation (read and write 16 for the data)

Application backgroundThis code is the subject of the research in the driver of a peripheral module, in order to read and write commands in the peripheral IIC bus transmission protocol, but because of the device's command and register state to the word as the unit, the general situation of the IIC b...

SPI_slave code, has been practical!

SPI_slave code, address length can be set to 1 ~ 3 bytes, the clock can run to 20MHz or more, has been used in the project, there is a need to be modified according to their own requirements!!!!...

FPGA implementation of SVPWM Technology

FPGA implementation of SVPWM technology, SVPWM signal waveform generation, dead time control, real-time requirements and other issues.SVPWM: space vector pulse width modulation (Vector Pulse Width Modulation Space)...

Gaussian Random number generator (hardware implemented)

This is hardware implemented Gaussian random number generator based on the article attached in the folder "Document" The system is based on the Ziggurat Gaussin random algorithm and implemented when I was under-graduate. Although it is not my original system, it is so helpful cause I can acquire a...

AD chip SPI interface configuration

Generated by the FPGA simulation of SPI interface timing, complete the AD chip configuration, AD chip of ADI company ad9852, program to configure more detailed, for using similar AD chip developer reference...

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