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Face detection system designed using verilog

Face detection is designed using verilog which is designed for the implementation on DE-2 FPGA board. This project is designed to detect the human face when the camera input detects a human....

Viterbi decoding works files

The goodies site search abroad, to share. Interior contains Verilog source code format. Has the reference value very much....

Verilog simulation filters

Verilog procedural simulation filters 16-order using the Adder and multiplier 40KHZ 16-bit into and out...

SRAM full--Verilog language

This code is based on Xilinx FPGA development platform, using Verilog language, full SRAM all functions. Has been tested to verify....

vedic multiplier 32 bit

design of high speed 32 bit vedic multiplier using vedic mahematics.this has a very less delay than other type of multipliers....

Design of 8 simple RISC-CPU

Reduced instruction set of the overall design and implementation of a simple 8-bit RISC CPU based functions, including addition, subtraction, and, or, XOR operation, RAM can also be read or write operations. In addition, there is RISC_CPU research paper, which contains a RISC-CPU design principle an...

Verilog code and simulation of Adaptive FIR filter waveforms

Adaptive filter means using the results of the previous time, the current time automatically adjust filter parameters, and the noise signal to accommodate changes in the characteristics of unknown or random, to obtain valid output, the design on the basis of MATLAB simulation using verilog achieve,...

Code verilog for motion compensated prediction block of video

This is a project about VLSI design.Topic is design for motion compensated prediction block in compressed video.Project consisted Code RTL,Code Testbench.  Project use software of synopsys for example: Design Compiler (Synthesis),IC Compiler (Layout)......

Non-restoring divider

Verilog code for a fixed point non-restoring divider for performing division of two 8-bit numbers. It works for unsigned numbers....

aes engine core

128 bit aes verilog code parallel aes engine for many core processor arrays...

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